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CY62157DV20 MoBL2
8M (512K x 16) Static RAM
Features
* * * * Very high speed: 55 ns Wide voltage range: 1.65V to 2.2V Pin compatible with CY62157CV18 Ultra low active power -- Typical active current: 1 mA @ f = 1 MHz -- Typical active current: 10 mA @ f = fmax Ultra low standby power Easy memory expansion with CE1, CE2 and OE features Automatic power-down when deselected CMOS for optimum speed/power Packages offered in a 48-ball FBGA deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
* * * * *
Functional Description[1]
The CY62157DV20 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
512K x 16 RAM ARRAY 2048 x 256 x 16
SENSE AMPS
I/O0 -I/O7 I/O8 -I/O15
COLUMN DECODER
A11 A12 A13 A14 A15 A16 A17 A18
BHE WE OE BLE
CE2 CE1
Power - down Circuit
BHE BLE
CE2 CE1
Note: 1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05136 Rev. *B
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised March 17, 2003
CY62157DV20 MoBL2
Pin Configuration[2, 3]
FBG A
1 BLE I/O 8 I/O 9 VSS VCC I/O 14 I/O 15 A18 2 OE BH E I/O 10 I/O 11 Top View 4 3 A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 C1 E I/O 1 I/O 3 I/O 4 I/O 5 WE A11 6 C2 E I/O 0 I/O 2 Vccq Vss q I/O 6 I/O 7 NC A B C D E F G H
I/O DNU 12 I/O 13 NC A8 A14 A 12 A9
Notes: 2. NC pins are not connected to the die. 3. DNU pins are to be connected to VSS or left open.
Document #: 38-05136 Rev. *B
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CY62157DV20 MoBL2
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential .-0.2V to VCCMAX + 0.2V DC Voltage Applied to Outputs in High-Z State[4] ................................... -0.2V to VCC + 0.2V DC Input Voltage[4] ................................ -0.2V to VCC + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Range Ambient Temperature (TA) VCC 1.65V to 2.2V Industrial -40C to +85C
Product Portfolio
Power Dissipation Operating, Icc (mA) VCC Range(V) Product CY62157DV20L CY62157DV20LL Min. 1.65 1.65 Typ.[5] 1.8 1.8 Max. 2.2 2.2 Speed (ns) 55 70 70 55 1 5 f = 1 MHz Typ.[5] 1 Max. 5 10 8 8 10 f = fMAX Typ.[5] Max. 20 15 15 20 Standby, ISB2 (A) Typ.[5] 2 2 2 2 Max. 25 25 17 17
DC Electrical Characteristics (Over the Operating Range)
CY62157DV20-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled Vcc = 2.2V, IOUT = 0 mA, CMOS level Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V 1.4 -0.2 -1 -1 10 1 2 2 Min. 1.4 0.2 VCC + 0.2 0.4 +1 +1 20 5 25 17 1.4 -0.2 -1 -1 8 1 2 2 Typ.[5] Max. CY62157DV20-70 Min. 1.4 0.2 VCC + 0.2 0.4 +1 +1 15 5 25 17 A Typ.[5] Max. Unit V V V V A A mA
VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz
ISB1
Automatic CE CE1 > VCC - 0.2V, CE2 < 0.2V, L Power-down Current - VIN > VCC - 0.2V, VIN < 0.2V, f LL CMOS Inputs = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) Automatic CE CE1 > VCC - 0.2V, CE2 < 0.2V, L Power-down Current - VIN > VCC - 0.2V or VIN < 0.2V, LL CMOS Inputs f = 0, VCC=2.2V Description Input Capacitance Output Capacitance
ISB2
2 2
25 17
2 2
25 17
A
Capacitance [6] Parameter CIN COUT
Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ)
Max. 6 8
Unit pF pF
Notes: 4. VIL(min.) = -2.0V for pulse durations less than 20 ns. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
Document #: 38-05136 Rev. *B
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CY62157DV20 MoBL2
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[6] Thermal Resistance (Junction to Case)[6] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 55 16 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT GND 30 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT R2 Rise Time: 1 V/ns Fall Time: 1 V/ns VCC Typ 10% ALL INPUT PULSES 90% 90% 10%
T HEVENIN EQUIVALENT
RTH
V
Parameters R1 R2 R TH VT H
1.8V 1350 0 1080 0 6000 0.80
UNIT V
Data Retention Characteristics
Parameter VDR ICCDR tCDR[6] tR[7]
b
Description VCC for Data Retention Data Retention Current
Conditions VCC = 1.0V, CE1 > VCC - 0.2V, CE2 L < 0.2V, VIN > VCC - 0.2V or VIN < LL 0.2V
Min. 1.0
Typ.[5] 1
Max. 2.2 10 3
Unit V A
Chip Deselect to Data Retention Time Operation Recovery Time
0 tRC
ns ns
Data Retention Waveform[8]
VCC CE1 or BHE . BLE or CE2
Notes: 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. . 8. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
VCC(min.) tCDR
DATA RETENTION MODE VDR > 1.0V
VCC(min.) tR
Document #: 38-05136 Rev. *B
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CY62157DV20 MoBL2
Switching Characteristics (Over the Operating Range)[9]
CY62157DV20-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[11] tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[13]
CY62157DV20-70 Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 5 25 70 60 60 0 0 50 60 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 10 ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW or CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[10] OE HIGH to High Z[10, 12] CE1 LOW or CE2 HIGH to Low Z[10] CE1 HIGH or CE2 LOW to High Z
[10, 12]
Min. 55
Max.
55 10 55 25 5 20 10 20 0 55 55 5 20 55 45 45 0 0 45 45 25 0 20 10
CE1 LOW or CE2 HIGH to Power-up CE1 HIGH or CE2 LOW to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[10] BLE/BHE HIGH to High Z[10, 12] Write Cycle Time CE1 LOW or CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z[10, 12] WE HIGH to Low Z[10]
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC ADDRESS tAA tOHA DAT A OUT PREVIOUS DATA VALID DATA VALID
Notes: 9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t 11. If both byte enables are toggled together, this value is 10 ns. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL. 14. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. 15. WE is HIGH for Read cycle.
Document #: 38-05136 Rev. *B
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CY62157DV20 MoBL2
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS t RC
C1 E
t PD t HZCE tACE
C2 E
BH E /BLE
t DBE t LZBE
OE
t HZBE
t DOE DAT A OUT VC C SUPPLY C URRENT tLZOE HIGH IMPEDANCE t LZCE tPU 50% DAT A VAL ID
t HZOE HIG H IMPEDANC E I CC I SB
50%
Write Cycle No. 1 (WE Controlled) [13, 17, 18, 19]
t WC ADDRESS tSCE C1 E C2 E tAW t SA W E t PWE t HA
BHE /BLE
tBW
O E tSD DATA I/ O
DON'T CARE
t HD
DATAIN V ALID t HZOE
Notes: 16. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. 17. Data I/O is high-impedance if OE = VIH. 18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05136 Rev. *B
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CY62157DV20 MoBL2
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 Controlled) [13, 17, 18, 19]
t WC ADDR E S S t SCE CE 1
CE 2
t SA
t AW t PWE
t HA
WE
B HE/B L E
t BW
OE t SD DAT AI/O
DON'T CARE
t HD
DAT AIN VAL I D t HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[18, 19]
tWC ADDRESS tSCE C1 E
C2 E tAW tSA WE tSD DATAI/O
DON'T CARE
tHA tPWE
tHD
DATA IN VALID tHZWE tLZWE
Document #: 38-05136 Rev. *B
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CY62157DV20 MoBL2
Switching Waveforms (continued)
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19]
t WC ADDR ESS
C1 E C2 E t SCE t AW t BW BH E /BLE t SA WE t PWE t SD DATA I/O
DON'T CARE
t HA
t HD
DATAIN VALID
Ordering Information
Speed (ns) 55 55 70 Ordering Code CY62157DV20L-55BVI CY62157DV20LL-55BVI CY62157DV20L-70BVI CY62157DV20LL-70BVI Package Name BV48A BV48A BV48A BV48A Package Type 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range Industrial Industrial Industrial
Document #: 38-05136 Rev. *B
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CY62157DV20 MoBL2
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
More Battery Life and MoBL2 are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05136 Rev. *B
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62157DV20 MoBL2
Document History Page
Document Title: CY62157DV20 MoBL2 512K x 16 Static RAM Document Number: 38-05136 REV. ** *A ECN NO. 115250 124693 Issue Date 05/29/02 03/18/03 Orig. of Change MGN DPM New Data Sheet Preliminary to Final Added Footnote 1 Added LL Bin to Iccdr value = 3 uA max Filled in TBD values Minor Change: Fixed incorrect footer on page 1 & 9. Description of Change
*B
124693
03/19/03
Dcon
Document #: 38-05136 Rev. *B
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